This invention relates generally to sample-and-hold circuits, and, more particularly, to sample-and-hold circuits that lend themselves to fabrication in monolithic form.
Recent advancements in integrated circuit technology have produced high-speed analog-to-digital converters in monolithic form. However, there has been no accompanying development of a corresponding high-speed integrated sample-and-hold circuit to provide analog input signals to an analog-to-digital converter. A typical high-speed sample-and-hold circuit of the prior art comprises an input amplifier, a capacitor, a switch for connecting a signal from the input amplifier to the capacitor, and an output amplifier for amplifying an output signal derived from the capacitor. The switch is typically a field effect transistor (FET) or a diode bridge driven by a transformer, the latter, of course, being a circuit element that cannot be produced in monolithic form. When the switch is closed, the voltage across the capacitor varies in accordance with the input signal, and this mode of operation is usually referred to as the tracking mode. When the switch is open, the capacitor preserves a signal sample corresponding to the level of the input signal at the time the switch is opened, and the circuit is then in a hold mode.
There are a number of design problems that can lead to significant inaccuracies in the operation of sample-and-hold circuits in general. For example, the output amplifier may draw a significant input current from the capacitor, resulting in a voltage droop when the switch is in the open condition and the circuit is in the hold mode. Another problem that may introduce errors while in the hold mode is that energy used to actuate the switch may be coupled onto the capacitor. Yet another problem in the hold mode is that the input analog signal may be capacitively coupled through the switch to the capacitor. Typically, there are other inaccuracies as well, due to linearity errors in the switch and amplifiers, settling time errors attributable to reactive parasitic impedances in leads between the components, and offset errors in the amplifier and the switch.
Sample-and-hold circuits of the general type with which the invention is concerned are either of discrete-component and hybrid, or monolithic construction. Discrete-component and hybrid construction both require relatively costly fabrication and assembly processes, as compared with monolithic fabrication. In addition, discrete-component sample-and-hold circuits cannot, in general, achieve a desirable level of performance. Certain types of hybrid circuits, using thin-film fabrication processes, have minimized many of the problems that lead to inaccuracy of performance, and have achieved high speeds of operation, but their cost is close to two orders of magnitude higher than monolithic circuits for performing the same function.
Monolithic sample-and-hold circuits are currently available from a number of manufacturers, but without exception, such circuits have, prior to this invention, utilized single-ended circuitry, typically employing operational amplifiers. Although these single-ended monolithic circuits are much less costly than the hybrid circuits discussed above, they are two to three orders of magnitude slower than the hybrid circuits. Accordingly, there has been a clear need for a monolithic sample-and-hold circuit which is much faster than such circuits already available, and which combines the advantages of low cost, high speed, and accuracy. The present invention is directed to this end.